In order to make more highly integrated semiconductor devices, a stacked semiconductor device structure has been developed that includes unit devices, such as MOS transistors, stacked on a substrate. In such stacked semiconductor devices, various semiconductor elements can be formed on respective levels, and therefore, the lengths of interconnections between elements may be decreased in comparison to non-stacked structures. The shortened interconnections may reduce interconnection resistance, which may improve high speed operation.
In some conventional stacked semiconductor devices, the semiconductor elements are formed at multiple levels. In particular, single-crystal silicon regions for formation of semiconductor elements may be formed on intervening interlevel insulating layers.
Various techniques have been proposed for forming single-crystal silicon regions on interlevel insulating layers. In one technique, a single-crystal silicon region may be formed by selective epitaxial growth using a single-crystal silicon substrate as a seed. However, selective epitaxial growth may require a significant amount of time and may have a relatively high process cost. Also, it may be difficult to form a single-crystal region over a large area using epitaxial growth.
In another technique, an insulating silicon oxide is formed on a single-crystal substrate with semiconductor unit elements formed thereon. After bonding another single-crystal silicon substrate onto the substrate, a single-crystal silicon region is formed by thinning the bonded single-crystal silicon substrate. Such bonding of crystalline silicon substrates may enable formation of a single-crystal silicon region over a wide area with relatively low cost. However, such a process may require use of patterning processes for forming active regions from the single-crystal silicon region. In other words, a separate photolithography process may be required to form single-crystal silicon patterns, which may make subsequent processes relatively complex.